Megatel Quark/100 Specifications download pdf (Page 24)

-----------------------_._--------------------------------------------

Summary

of Shift Register input

modes

(ACR-4

=

0)

ACR-3

ACR-2

Remarks

o

o

1

1

o

1

o

1

Shift

register

disabled.

8

bits

only shifted

in

at

T2

rate.

SR

Interrupt

Flag

set

after

8

bits

shifted.

Shift pulses generated

on

CB1

during

shifting.

8

bits

only shifted in

at

E-clock

rate.

SR

Interrupt

Flag

set

after

8

bits

shifted.

Shift pulses generated

on

CB1

during

shifting.

8

bits

or

more

shifted at

CB1

input

rate.

SR

Interrupt

Flag

set

each

time 8

bits

shifted

in.

Install

J3

&

J4

for

Timer

1 clock to

CB1

input.

In the

first

mode

(ACR-2=0,

ACR-3=O)

the

SR

is disabLed.

The

SR

can

be

read or written,

but

no

shifting

occurs,

and

the

CB1

and

CB2

lines are

under

the control of the appropriate

bits

in

the Peripheral Control Register.

In the next

mode

(ACR-2=1,

ACR-3=0),

data is shifted into the

SR

at

a rate controlled

by

Timer

2.

Shift pulses are generated

on

the

CB1

1 ine.

If

JS

is

installed,

then these pulses

will

appear

(at

RS-232C

signal

levels)

on

pin

A-4

of

the

connector. (Note

that

if

J4

is

insta lled, these pulses, at

TTL

signal levels,

wi

II also appear

on

the Receive

Clock

input of

the

ACIA.

This

may

interfere

with the operation of the

ACI~)

The

third

mode

is

similar

to the previous, except that the E-clock

is

used

to control the

shi

ft

rate.

In the

final

mode,

pulses

on

the

CB1

Line

control the

shift

rate.

The

only

way

to provide

a signal input to the

CB1

line while

CB2

is

being

used

for the

SR

input

is

to

install

J3

and

J4. This connects the

PB7

line to the Transmit

and

Receive

clocks

of

the

ACIA

and

to the

CB1

input. This allows

Timer

1

to

generate a clock

signaL

for the

ACIA

and

for the

Shift

Register.

Values

for

Timer

1 to generate

commonly-used

baud

rates for the Simplex Port are given

in

Table

IV.

By

various combinations of

straps,

the lines

and

RS-232C

drivers

and

receivers associated

with

this

port

may

be

used

for a variety of purposes.

Parallel

I/O lines

--------------------_._._------------------

The

QUARK

provides fourteen general-purpose

I/O

lines

(not

including the nine lines

on

the

PIA

used

for the paralLel

keyboard

interface).

These

lines are connected

to

Ports A

and

B of

the

VIA.

Each

of these lines

may

be

programmed

to act

as

an

input or

as

an

output

by

setting

or clearing the corresponding

bit

in

the

Data

Direction Register.

ParalleL Port 2 of the

QUARK

provides eight

I/O

lines.

These

are connected

to

the

PAO

to

PA7

lines

on

the

VIA.

These

lines are

not

dedi

cated to

any

parti cular purpose in the system

software for the

QUARK.

ParalLel Port 3 of the

QUARK

provides six

I/O

lines,

which

are connected

to

the

PBO

to

PBS

Lines.

Under

the standard

distributed

operating system, the

PBO

line is configured as the

'bell"

output

from

the

QUARK.

When

an

ASCII

control-G character

(code

07)

is

encountered

by

the terminal driver, a square

wave

wi

II be

produced

on

this

output.

The

PBO

output

Line

may

be

capable of driving

some

piezo-electric acoustic transducers

directly,

or

an

external buffer

ampLifier using a

transistor

or gate

can

be

used

to drive a small speaker.

The

two

remaining I/O lines of Port B

on

the

VIA

are intended for

some

specific uses.

PB7

is normally

used

as

the output line for

Timer

1-generated baud rates for the

FuLL-DupLex

SeriaL

Megatel

Computer

TechnoLogies

Toronto,

Canada

Page

H/W-19

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