Megatel Quark/100 Specifications Page 28

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The
Z8OB's
Interrupt input line
awn
is avai lable
on
the Peripheral
Expansion
Bus
to
allow external devices to generate interrupts to the
Z8OB.
A
power-on
reset output (active
low)
is also provided to reset external peripheral devices. Finally, a
decoded
active-low chip-
select line responding to
1/0
addresses
between
CO
and
FF(hex)
is
created on-board
and
can
be
used
to select a single external peripheral device, or to qualify the decoding of
some
of the
address lines for several external chip-select lines.
The
Power-on-reset
~
output
on
the Peripheral
Expansion
Bus
is
an
active-low buffered
reset line
which
should
be
used
in
resetting external peripheral devices.
Note
that
808D-type
devi
ces
requi
re
an
active-high reset signal,
so
the
POR
line
would
have
to
be
inverted
to
service these devices.
To
ease
timing
requirements
for
interfacing
external
peripheral
devices
to
the
six
megahertz
CPU,
four wait
states
(T-states) are
added
to
all
zao
1/0
machine
cycles. This
is
over
and
above the standard
extension
to
mod-4
cycles
for
any
memory
cycle.
Thus
an
1/0
instruction
which
might
require, for example,
10
cycles
would
be
first
extended
to
12
cycles,
and
then further extend to
16
cycles. This allows
"AU-version
(1.5MHz)
peripheral devices to
be
used. Because of
the
exact
rule
used
for
wait-state
insertion,
Table
XII
should
be
consulted for precise instruction timing information.
If
several external peripheral devi
ces
are to be connected to the
QUARK's
Peripheral
Expansion
Bus,
or
if
the
Bus
is to
be
extended
any
significant distance,
it
is
recommended
that
the address, data,
and
control lines being
used
be buffered
by
TIL
drivers.
Two
TTL
packages
are sufficient for
this
purpose
if
only
8080-
or only 6500/680D-type peripheral chips are used;
if
both
types are
employed
then
an
additional buffer
is
necessary, unless five or fewer address
lines are
reCJ.Iired.
An
application rote
on
use
of
this
bus
is
available.
Megatel
Computer
Technologies Toronto,
Canada
Page
H/W-23
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