Megatel Quark/100 Specifications Page 69

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3.
where
fE
is
the frequency of the E-clock
and
N
is
the value in the
Timer
2 latch.
Connectlng
jumpers
J3
and
J4
will connect the
PB7
I/O
line
from
the
VIA
to
the
CB1
control
line of the
VIA.
This
allows
Timer
1,
normally
used
to generate the transmit
and
receive
clocks for the full-duplex
serial
port, to generate the
simplex
serial
port clock
as
well. I
However,
split
baud
rates
on
the full-duplex channel are
not
possible
when
Timer
1
is
used
in
this
way.
---
--
TABLE
V
SYNCHRONOUS
ADDRESS
MULTIPLEXER
ADDRESS
ASSIGNMENTS
ADDRESS
CONTROL
REGISTER
SET/CLEAR
REMARKS
(HEX)
BIT
---------
------
-
FFBO
va
CLR
Norma
lly c lea
red
FF81
va
SET
FF82
V1
CLR
Normally
cleared
FF83
V1
SET
FF84
V2
CLR
Cleared for
Alphanumeric
Mode
FF85
V2
SET
Set for Graphics
Mode
FF86
Fa
CLR
Start
address
bit
10
FF87
FO
SET
FF88
F1
CLR
Start address
bit
11
FF89
F1
SET
FFSA
F2
CLR
Start
address
bit
12
FF8B
F2
SET
FF8C
F3
CLR
Start address
bit
13
FF8D
F3
SET
FF8E
F4
CLR
Norma
lly set
FF8F
F4
SET
FF90
F5
CLR
Start address
bit
14
FF91
F5
SET
FF92
F6
CLR
Start
address
bit
15
FF93
F6
SET
FF94
P1
CLR
Page
bit
FF95
P1
SET
FF96
Ra
CLR
Norma
lly cleared
FF97
RO
SET
FF98
R1
CLR
Norma
lly c lea
red
FF99
R1
SET
FF9A
Ma
CLR
Norma
lly cleared
FF9B
MO
SET
FF9C
M1
CLR
Norma
lly set
FF9D
M1
SET
FF9E
TV
CLR
Map
type-see sec
T/1.1
FF9F
TV
SET
(Norma
lly
set)
Notes:
1.
To
set or clear
any
of
the
bits
in
SAM
registers,
load
the address in the
above
table
corresponding to the
bit
to
be
set
or
cleared into the
HL
register,
and
then execute a
CALL
to
the subroutine at location
OBhex.
(Note
that
this
routine
alters
the contents of
the
C
register.)
-_._---------_.---_._._--------------
Megatel
Computer
Technologies Toronto,
Canada
Appendix
Page
A-8
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