Megatel Quark/100 Specifications download pdf (Page 11)

QUARK

Video Display

Memory

--------,------------------------------,---------------------------------------

The

size

of

the

Video Display

Memory

and

its

location

within

the

128k

Main

Memory

are

under

the

control

of

registers

in

the

SAM

and

by

bit

0

of

the

I-register.

Bit

0

of

the

I-register

determines

in

which

memory

bank

the

Video Display

Memory

is

located.

When

this

bit

is

clear,

the

Video Display

Memory

is

located

entirely

within

bank

A,

and

when

it

is

set,

the

Video Display

Memory

is

located

entirely

within

bank

B.

The

bank

switching

apparatus

for

the

Main

Memory

using

bits

S-7

of

the

I-register

does not

apply

to

addresses

generated

by

the

Video Display

Controller,

but only

to

addresses

generated

by

the

CPU,

regardless

of

whether

these

CPU

addresses

fall

within

the

Video Display

Memory

or

not.

In

either

bank A

or

bank

B,

the

physi

cal

address

boundaries

of

the

Video Display

memory

within

the

selected

bank

are

determined

by

the

settings

of

bits

F0,

F1, F2,

F3,

FS,

and

F6

in

the

SAM

control

Register,

and

by

the

Video Display

Mode

(ALPHA

or

GRAPHICS).

The

starting

address

(or

the

lower bound)

of

the

Video Display

Memory

is

the

binary

address

(F6)(FS) (F3)(F2)

(F1

)(FCI

)Cla

(laCia

aaaa,

where

(Fn)

represents

the

contents

on

the

Fn

bit

in

the

SAM

Control

Register.

The

final

address

(or

the

upper bound)

of

the

Video Display

Memory

depends

on

the

Video Display

Mode.

In

Alphanumeric

Mode,

the

final

address

is

the

first

16k

address

boundary followimg

the

starting

address,

whereas

in

Graphics

Mode,

the

final

address

is

the

second

16k

address

boundary

following

the

starting

address.

From

the

above,

it

can be

seen

that

the

size

of

the

Video

Display

Memory

may

be

set

anywhere from

zero

to

32k in 1024-byte

increments.

However, only a

certain

set

of

sizes

are

likely

to

be

of

use in most

applications.

First,

when

operating

in

Graphics mode,

the

size

of

the

Video

Display

memory must be an

integer

multiple

of

3k (3072)

bytes

in

order

for

the

horizontal

sync

signal

to

be

generated

correctly.

Second,

if

it

is

desired

to

have

the

Vertical

Sync

fre~ency

match

the

fre~ency

of

the

local

AC

power system

(to

avoid moving "hum-

bars"

on

the

CRT

and

related

phenomena),

the

size

of

the

Video Display

Memory

must be

adjusted

so

that

its

entire

contents

wi

II

be read and

displayed

once

during

one

cycle

of

the

AC

power

line.

In

practice,

this

means

that

the

most

useful

sizes

are

likely

to

be:

LIN:

FREQ.

MODE

SIZE

----------_.----------.-----

50Hz

50Hz

60Hz

60Hz

ALPHA

Sk

GRAPHIC

30k

ALPHA

4k

GRAPHIC

24k

In

order

to

achieve

a

Vertical

Sync

frequency

of

exactly

50

Hz

or

60Hz,

it

is

necessary

that

the

appropriate

frequency

crystal

be used in

the

Master Clock

generato~

Thus

it

is

not

possible

to

generate

a

50Hz

vertical

sync frequency

on

a board equipped

with

a

crystal

intended

to

~ermit

operation

at

60Hz,

and

vice

versa.

However, a

"60Hz"

QUARK

can be programmed

to

operate

with a

Vertical

Sync

fre~ency

of

48.1Hz, and a

"50Hz"

QUARK

can be

operated

at

62.5Hz.

See Table

VI

in

the

Appendix

for

suggested

settings

and

the

resultant

address

ranges.

Note

that

the

F4

bit

in

the

SAM

in not used

in

determining

the

starting

address

of

the

Video Display

Memory,

and must always be

set.

Bits

1 through 4

of

the

I-register

are

"don't

care"

bi

ts,

and have

no

effect

on

the

ope

rat

i

on

of

the

QUARK.

Megatel Computer Technologies

Toronto,

Canada

Page

H/W-7

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