Megatel Quark/100 Specifications download pdf (Page 22)

order latch (I/O address

68hex)

to produce

commonly-used

baud

rates

can

be

found

in Table

III(a)

and

III(b)

in

the

Appendix. Jumpers J5

and

J6 should not both

be

installed

when

attempting to

use

split

baud

rates,

or the Shift Register output

on

CB2

will

short out the

T2-

generated clock output

00

CB1.

To

enable

this

Shift Register

Mode,

the

Auxi

liary

Control Register

(ACR,

I/O

address

6Bhex)

of the

VIA

must

be

written with

bits

2

and

3

low

and

bit

4 high.

According

to

the

manufacturer's data sheet for the

VIA,

it

is also necessary to perform

an

I/O

read or write

operatioo to the

SR

after

setting

~

the Shift

Mode

to

start

the clocking of the

SR

(and

the

clock

pJlse output

00

CB1).

Note

that using

Timer

2

and

the

Shift

Register for

this

purpose

precludes the

use

of the

Simplex

Serial Port,

which

uses the

VIA's

Shift Register,

as

a

serial

data

channe

l.

Although Timer 2 uses a

16-bit

counter,

only the

least-significant

eight

bits

are

automatically re-loaded

in

its

free-run

mode.

Thus,

the

range

of

baud

rates

directly

available

from

this

timer is

more

limited than that

of

Timer

1.

However,

this

range

can

be

extended

by

using the divide-by-16

and

divide-by-64

modes

of the

ACI~

Note

that the divide

ratio

selected

applies to

both

the Transmit

and

Receive clocks. Table

IV

gives the values for the

Timer

2

latch required for

commoo

baud

rates.

The

period of the basic clock signal generated

by

Timer

2

is

given

by

(2N+4)

* t

E

,

where

tE

is

the period of the system E-clock (given previousLy)

and

N

is

the value in the

Timer

2

LatcH.

Note

that

on

the

QUARK

the

negative

supply

voltage

used

for

the

RS-232C

drivers

is

developed on-card

by

a

charge-pump

circuit.

As

a

result,

the

voLtage

swing

on

the

RS-232C

outputs is usuaLly in the

range

of

+11V

to

-BV.

Simplex

Serial

Interface

In

additioo to the Full-Duplex Serial Port, the

QUARK

provides a simplex (unidirectional)

asynchronous

serial

data port. This port uses the Shift Register of the

VIA

(part

number

6522A)

and

includes line drivers

and

receivers for compatibiLty with

RS-232C

signal

LeveLs.

The

SimpLex

Port

aLLows

the

QUARK

to

be

connected

to

receive-only

or

transmit-only

peripheraLs with seriaL interfaces,

such

as

printers

or seriaL-output

encoded

keyboards.

The

port

can

also

be

used

for other pJrposes,

such

as

generating tones.

By

means

of jumpers J5-S,

the port

can

be

configured for

serial

output or input

(but

not both).

One

protocol line

is

also provided.

Depending

00

which

jumpers are

installed,

this

protocol line

may

be

used

as

an

input

or

an

output.

For

serial

output, the Shift Register

(SR),

the

CB2

control

line,

and

the

PB6

I/O

line of

the

-VIA

are used.

In

this

mode,

data in the

shift

register

is

shifted out

on

the

CB2

pin of

the

VIA.

With

J6

installed

(done

at the factory

unLess

ordered otherwise), the

serial

data

is

shifted

to

RS232C

output voltage

leveLs

and

is

avai lable

on

pin

A-4

of the

QUARK's

connector.

The

protocoL

Line,

an

RS-232C

compatibLe

input for

this

mode,

is

pin

B-2.

Jumper

JS

(also

instalLed at the factory) allows the

state

of the protocol

Line

to

be

read

00

the

PB6

I/O line

of the

VIA.

Bit 6 in

Data

Direction Register B of the

VIA

must

be

zero

to

aLLow

the

use

of

PB6

as

an

input.

In order for the

Shift Register to

be

used

in

the output

mode,

bit

4 in the

Auxi

LL

iary

ControL

Register

(ACR)

of the

VIA

must

be

set.

With

this

bit

set,

bits

2

and

3 of the

ACR

will

determine the rate at

which

the

SR

is

shifted,

as

weLL

as

its

operational

mode.

MegateL

Computer

TechnoLogies

Toronto,

Canada

Page

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